Prosecution Insights
Prosecution Insights
41 pending office actions • 1 client • 35 examiners • 22 art units • 0 of 41 (0%) have an AI response strategy ready • 183 patents granted in the last 365 days
Based on the USPTO statutory response window for each pending office action. 41 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 41 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 26 (63%) |
| §102 only | 9 (22%) |
| §112 only | 3 (7%) |
| No statute on record | 3 (7%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| TRA, ANH QUAN | 2 | 72.7% | +5.5% |
| BEGUM, SULTANA | 2 | 93.3% | +0.4% |
| TAT, BINH C | 2 | 87.3% | +14.1% |
| MICHAUD, NICHOLAS BRIAN | 2 | 73.6% | +30.2% |
| PILLAY, DEVINA | 2 | 44.1% | +26.7% |
| LIN, ARIC | 2 | 60.0% | +12.9% |
| KNAPP, JUSTIN R | 1 | 84.6% | +8.2% |
| JOHNSON, AMY COHEN | 1 | 55.4% | +22.2% |
| LEONG, NATHAN T | 1 | 70.9% | +24.5% |
| KIM, JUNG H | 1 | 88.5% | +6.2% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 5 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18767858 | CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER | BEGUM, SULTANA | 59d overdue |
| 18587437 | SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM | TAT, BINH C | 31d overdue |
| 18760589 | END-OF-CYCLE SIGNAL GENERATION CIRCUIT AND METHOD | BEGUM, SULTANA | 17d overdue |
| 18789505 | METHODS OF MANUFACTURING FLIP-FLOP WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES AND SEMICONDUCTOR DEVICE INCLUDING SAME | KIM, JUNG H | 7d |
| 17834606 | INTEGRATED CIRCUIT (IC) DESIGN METHODS USING PROCESS FRIENDLY CELL ARCHITECTURES | TAT, BINH C | 16d |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 8 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17220269 | INTEGRATED CIRCUIT STRUCTURE | LIN, ARIC | 58d overdue |
| 17111014 | INTEGRATED CIRCUIT LAYOUT DIAGRAM SYSTEM | LIN, ARIC | 58d overdue |
| 17857467 | THERMOELECTRIC STRUCTURE AND MANUFACTURING METHOD | PILLAY, DEVINA | 46d overdue |
| 17203221 | THERMOELECTRIC STRUCTURE AND METHOD | PILLAY, DEVINA | 46d overdue |
| 18587437 | SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM | TAT, BINH C | 31d overdue |
| 18447737 | METHOD OF MAKING SEMICONDUCTOR DEVICE HAVING BURIED BIAS PAD | MICHAUD, NICHOLAS BRIAN | 16d overdue |
| 18447614 | METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE | MICHAUD, NICHOLAS BRIAN | 3d overdue |
| 18790296 | METHOD AND APPARATUS FOR LOGIC CELL-BASED PUF GENERATORS | JOHNSON, AMY COHEN | 7d |
| Client (Assignee) | Pending OAs |
|---|---|
| TSMC | 41 |
| Art Unit | Apps |
|---|---|
| 2851 | 7 |
| 2812 | 4 |
| 2825 | 3 |
| 2818 | 3 |
| 2843 | 2 |
| 2824 | 2 |
| 2891 | 2 |
| 2898 | 2 |
| 2893 | 2 |
| 1726 | 2 |
| App # | Title | Client | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|---|
| 18936254 | MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME | Taiwan Semiconductor Manufacturing Company, Ltd. | KNAPP, JUSTIN R | 2112 | Other | Non-Final OA | 16d overdue | Pending | Nov 04, 2024 |
| 18791080 | DECOUPLING CAPACITOR CIRCUITS | Taiwan Semiconductor Manufacturing Company, Ltd. | TRA, ANH QUAN | 2843 | §103 | Non-Final OA | 9d overdue | Pending | Jul 31, 2024 |
| 18790296 | METHOD AND APPARATUS FOR LOGIC CELL-BASED PUF GENERATORS | Taiwan Semiconductor Manufacturing Co., Ltd. | JOHNSON, AMY COHEN | 2400 | Other | Non-Final OA | 7d | Pending | Jul 31, 2024 |
| 18789582 | SYSTEM, APPARATUS, AND METHOD FOR IMPROVING PHOTORESIST COATING OPERATIONS | Tsmc Nanjing Company, Limited | LEONG, NATHAN T | 1718 | §103 | Non-Final OA | 9d | Pending | Jul 30, 2024 |
| 18789505 | METHODS OF MANUFACTURING FLIP-FLOP WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES AND SEMICONDUCTOR DEVICE INCLUDING SAME | Tsmc Nanjing Company, Limited | KIM, JUNG H | 2842 | §103 | Non-Final OA | 7d | Pending | Jul 30, 2024 |
| 18777324 | CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME | Taiwan Semiconductor Manufacturing Company, Ltd. | CRAWFORD, JASON | 2844 | §103 | Non-Final OA | 30d overdue | Pending | Jul 18, 2024 |
| 18771863 | MEMORY CELL ARRAY AND METHOD OF OPERATING SAME | Taiwan Semiconductor Manufacturing Company, Ltd. | CHO, SUNG IL | 2825 | §103 | Non-Final OA | 35d overdue | Pending | Jul 12, 2024 |
| 18767858 | CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER | Taiwan Semiconductor Manufacturing Co., Ltd. | BEGUM, SULTANA | 2824 | §103 | Non-Final OA | 59d overdue | Pending | Jul 09, 2024 |
| 18760589 | END-OF-CYCLE SIGNAL GENERATION CIRCUIT AND METHOD | Taiwan Semiconductor Manufacturing Company, Ltd. | BEGUM, SULTANA | 2824 | §112 | Non-Final OA | 17d overdue | Pending | Jul 01, 2024 |
| 18754948 | SEMICONDUCTOR INTEGRATED CIRCUIT | Taiwan Semiconductor Manufacturing Company, Ltd. | ERDEM, FAZLI | 2812 | §103 | Non-Final OA | 12d | Pending | Jun 26, 2024 |
| 18734190 | SEMICONDUCTOR STRUCTURE HAVING A BUTTED CONTACT AND METHOD OF FORMING | Taiwan Semiconductor Manufacturing Company, Ltd. | SALERNO, SARAH KATE | 2814 | §102 | Non-Final OA | 9d | Pending | Jun 05, 2024 |
| 18623806 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SAME | Taiwan Semiconductor Manufacturing Company, Ltd. | GONDARENKO, NATALIA A | 2891 | §103 | Non-Final OA | 27d | Pending | Apr 01, 2024 |
| 18601191 | SLOW WAVE INDUCTIVE STRUCTURE | Taiwan Semiconductor Manufacturing Company, Ltd. | HINSON, RONALD | 2837 | §103 | Non-Final OA | 36d overdue | Pending | Mar 11, 2024 |
| 18587437 | SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM | Taiwan Semiconductor Manufacturing Company, Ltd. | TAT, BINH C | 2851 | §102 | Non-Final OA | 31d overdue | Pending | Feb 26, 2024 |
| 18507817 | POST PASSIVATION INTERCONNECT | Taiwan Semiconductor Manufacturing Company, Ltd. | ASSOUMAN, HERVE-LOUIS Y | 2812 | §102 | Non-Final OA | 33d | Pending | Nov 13, 2023 |
| 18498369 | INTEGRATED CIRCUIT, SYSTEM AND METHOD OF FORMING THE SAME | Taiwan Semiconductor Manufacturing Company, Ltd. | WELLS, JAMES STEVEN | 2825 | §103 | Non-Final OA | 77d overdue | Pending | Oct 31, 2023 |
| 18453162 | POWER TAP CONNECTIONS FOR NON-CMOS CIRCUITS UTILIZING CFET TECHNOLOGY | Taiwan Semiconductor Manufacturing Company, Ltd. | RODRIGUEZ VILLANU, SANDRA MILENA | 2898 | §103 | Non-Final OA | 23d | Pending | Aug 21, 2023 |
| 18448125 | DIAGONAL VIA STRUCTURE | Taiwan Semiconductor Manufacturing Company, Ltd. | ZARNEKE, DAVID A | 2891 | §103 | Non-Final OA | 20d | Pending | Aug 10, 2023 |
| 18448013 | SUPER JUNCTION STRUCTURE | Taiwan Semiconductor Manufacturing Company, Ltd. | MIYOSHI, JESSE Y | 2898 | §103 | Non-Final OA | 50d overdue | Pending | Aug 10, 2023 |
| 18447614 | METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE | Taiwan Semiconductor Manufacturing Company, Ltd. | MICHAUD, NICHOLAS BRIAN | 2818 | §103 | Non-Final OA | 3d overdue | Pending | Aug 10, 2023 |
| 18447979 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME | Taiwan Semiconductor Manufacturing Company, Ltd. | SEDOROOK, DAVID PAUL | 2812 | §103 | Non-Final OA | 42d overdue | Pending | Aug 10, 2023 |
| 18447737 | METHOD OF MAKING SEMICONDUCTOR DEVICE HAVING BURIED BIAS PAD | Tsmc China Company, Limited | MICHAUD, NICHOLAS BRIAN | 2818 | §112 | Non-Final OA | 16d overdue | Pending | Aug 10, 2023 |
| 18362873 | SEMICONDUCTOR DEVICE HAVING MULTIPLE WELLS | Taiwan Semiconductor Manufacturing Company, Ltd. | AHMED, SHAHED | 2813 | §103 | Non-Final OA | 39d | Pending | Jul 31, 2023 |
| 18358239 | RESISTIVE-NETWORK CELL REGION, BUILT-IN SELF-TESTER INCLUDING SAME, SEMICONDUCTOR DEVICE INCLUDING SAME, METHOD OF OPERATING SAME AND METHOD OF MANUFACTURING SAME | Tsmc China Company, Limited | MAHONEY, CHRISTOPHER E | 2852 | §102 | Non-Final OA | 5d overdue | Pending | Jul 25, 2023 |
| 18343425 | DUAL MODE SUPPLY CIRCUIT AND METHOD | Tsmc China Company, Limited | TRAN, NGUYEN | 2838 | §103 | Non-Final OA | 55d | Pending | Jun 28, 2023 |
| 18337267 | STACKED TRANSISTORS IN MEMORY CIRCUIT AND METHOD OF OPERATING SAME | Taiwan Semiconductor Manufacturing Company, Ltd. | BERMUDEZ LOZADA, ALFREDO | 2825 | §103 | Non-Final OA | 46d overdue | Pending | Jun 19, 2023 |
| 18314555 | LEAKAGE REDUCTION BY HALO-IMP TECHNOLOGY IN MESA REGION OF NANO SHEET DEVICE | Taiwan Semiconductor Manufacturing Company, Ltd. | HAN, JONATHAN | 2818 | §102 | Non-Final OA | 4d overdue | Pending | May 09, 2023 |
| 18128601 | INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME | Taiwan Semiconductor Manufacturing Company, Ltd. | GREWAL, HEIM KIRIN | 2812 | §103 | Non-Final OA | 17d overdue | Pending | Mar 30, 2023 |
| 18185059 | CHARGE PUMP CIRCUIT AND METHOD | Taiwan Semiconductor Manufacturing Company, Ltd. | TRA, ANH QUAN | 2843 | §103 | Non-Final OA | 70d overdue | Pending | Mar 16, 2023 |
| 18170111 | INTEGRATED CIRCUIT DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT | Taiwan Semiconductor Manufacturing Company, Ltd. | PARIHAR, SUCHIN | 2851 | §102 | Non-Final OA | 12d | Pending | Feb 16, 2023 |
| 18165292 | METHOD OF EXECUTING DESIGN FLOW WITH MACHINE LEARNING TECHNIQUES | Taiwan Semiconductor Manufacturing Company, Ltd. | NGUYEN, NHA T | 2851 | §102 | Non-Final OA | 2d overdue | Pending | Feb 06, 2023 |
| 18160593 | INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM | Taiwan Semiconductor Manufacturing Company, Ltd. | DINH, PAUL | 2851 | §102 | Non-Final OA | 53d overdue | Pending | Jan 27, 2023 |
| 17976313 | VERTICAL NOISE REDUCTION IN 3D STACKED SEMICONDUCTOR DEVICES | Taiwan Semiconductor Manufacturing Co., Ltd. | WHALEN, DANIEL B | 2893 | Other | Final Rejection | 57d | Pending | Oct 28, 2022 |
| 17857467 | THERMOELECTRIC STRUCTURE AND MANUFACTURING METHOD | Taiwan Semiconductor Manufacturing Company, Ltd. | PILLAY, DEVINA | 1726 | §103 | Non-Final OA | 46d overdue | Pending | Jul 05, 2022 |
| 17851569 | SEMICONDUCTOR DEVICE INCLUDING ANTI-FUSE CELL STRUCTURE | Taiwan Semiconductor Manufacturing Company, Ltd. | SENGDARA, VONGSAVANH | 2893 | §103 | Non-Final OA | 53d overdue | Pending | Jun 28, 2022 |
| 17834606 | INTEGRATED CIRCUIT (IC) DESIGN METHODS USING PROCESS FRIENDLY CELL ARCHITECTURES | Taiwan Semiconductor Manufacturing Co., Ltd. | TAT, BINH C | 2851 | §102 | Final Rejection | 16d | Pending | Jun 07, 2022 |
| 17575578 | DEVICE LEVEL THERMAL DISSIPATION | Taiwan Semiconductor Manufacturing Company, Ltd. | CHEN, YU | 2896 | §103 | Non-Final OA | 162d overdue | Pending | Jan 13, 2022 |
| 17335985 | SEMICONDUCTOR PACKAGE AND METHOD OF MAKING | Taiwan Semiconductor Manufacturing Company, Ltd. | LI, MEIYA | 2811 | §112 | Non-Final OA | 22d | Pending | Jun 01, 2021 |
| 17220269 | INTEGRATED CIRCUIT STRUCTURE | Taiwan Semiconductor Manufacturing Company, Ltd. | LIN, ARIC | 2851 | §103 | Final Rejection | 58d overdue | Pending | Apr 01, 2021 |
| 17203221 | THERMOELECTRIC STRUCTURE AND METHOD | Taiwan Semiconductor Manufacturing Company, Ltd. | PILLAY, DEVINA | 1726 | §103 | Non-Final OA | 46d overdue | Pending | Mar 16, 2021 |
| 17111014 | INTEGRATED CIRCUIT LAYOUT DIAGRAM SYSTEM | Taiwan Semiconductor Manufacturing Company, Ltd. | LIN, ARIC | 2851 | §103 | Final Rejection | 58d overdue | Pending | Dec 03, 2020 |
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