120 pending office actions • 5 clients • 113 examiners • 36 art units • 95 of 120 (79%) have an AI response strategy ready • 273 patents granted in the last 365 days
Based on the USPTO statutory response window for each pending office action. 120 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 120 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §101 + other | 1 (1%) |
| §103 only | 57 (48%) |
| §102 only | 7 (6%) |
| §112 only | 3 (2%) |
| Double-patenting + other | 4 (3%) |
| Multi-statute (no §101) | 48 (40%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| MUNOZ, ANDRES F | 2 | 76.5% | +18.1% |
| VALENZUELA, PATRICIA D | 2 | 90.2% | +2.1% |
| KOO, LAMONT B | 2 | 80.5% | +4.9% |
| TRAN, TRANG Q | 2 | 80.9% | +7.0% |
| ENAD, CHRISTINE A | 2 | 84.2% | +10.2% |
| TURNER, BRIAN | 2 | 83.0% | +4.5% |
| JUNGE, BRYAN R. | 2 | 57.7% | +9.0% |
| STRAUB, D'ARCY WINSTON | 1 | 77.6% | +18.8% |
| LEE, LAURA MICHELLE | 1 | 54.8% | +30.9% |
| NGUYEN, JIMMY T | 1 | 76.8% | +23.7% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 5 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17851985 | INTEGRATED CIRCUIT STRUCTURES HAVING MEMORY WITH BACKSIDE POWER DELIVERY | TURNER, BRIAN | 30d overdue |
| 18438450 | INTEGRATED TOP SIDE POWER DELIVERY THERMAL TECHNOLOGY | VALENZUELA, PATRICIA D | 34d |
| 17954194 | INTEGRATED CIRCUIT STRUCTURES HAVING FIN ISOLATION REGIONS BOUND BY GATE CUTS | ENAD, CHRISTINE A | 34d |
| 18242322 | PACKAGE WITH EMBEDDED CAPACITORS | TRAN, TRANG Q | 55d |
| 17855636 | VOLTAGE CONTRAST SCAN AREA ON A WAFER | VALENZUELA, PATRICIA D | 79d |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 8 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17020200 | TANDEM MAGNETICS IN PACKAGE | CHAN, TSZFUNG JACKIE | 98d overdue |
| 17481234 | MULTIPLE DIES COUPLED WITH A GLASS CORE SUBSTRATE | TRAN, TRANG Q | 80d overdue |
| 18072564 | FABRICATION OF INTEGRATED CIRCUIT STRUCTURES HAVING UNIFORMITY AMONG VARYING GATE TRENCH WIDTHS | BEARDSLEY, JONAS TYLER | 45d overdue |
| 17554442 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING RAISED WALL STRUCTURES FOR EPITAXIAL SOURCE OR DRAIN REGION CONFINEMENT | ADHIKARI DAWADI, BIPANA | 45d overdue |
| 17853500 | IN-SITU MULTI-LAYER DIELECTRIC FILMS FOR APPLICATION AS GATE SPACER AND ETCH STOP LAYERS | DUREN, TIMOTHY EDWARD | 44d overdue |
| 17953206 | ELECTROLYTIC SURFACE FINISH ARCHITECTURE | ROBINSON, KRYSTAL | 28d overdue |
| 17887273 | SACRIFICIAL LAYER FOR SUBSTRATE ANALYSIS | BODNAR, JOHN A | 28d overdue |
| 18088542 | GALLIUM NITRIDE (GAN) LAYER ON SUBSTRATE CARBURIZATION FOR INTEGRATED CIRCUIT TECHNOLOGY | TYNES JR., LAWRENCE C | 26d overdue |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 7 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18654739 | SAWMILL CARRIAGE, SAWMILL CARRIAGE KIT, AND METHOD OF USING SAME | LEE, LAURA MICHELLE | 30d overdue |
| 17710802 | DEVICE PERFORMANCE TUNING BY DEEP TRENCH VIA (DVB) PROXIMITY EFFECT IN ARCHITECTURE OF BACKSIDE POWER DELIVERY | ENAD, CHRISTINE A | 15d overdue |
| 18896711 | PRIVACY SUPPORTING MESSAGING SYSTEMS AND METHODS | STRAUB, D'ARCY WINSTON | 5d overdue |
| 17553161 | INTEGRATED CIRCUIT STRUCTURES HAVING DIELECTRIC ANCHOR AND CONFINED EPITAXIAL SOURCE OR DRAIN STRUCTURE | MUNOZ, ANDRES F | 9d |
| 17954194 | INTEGRATED CIRCUIT STRUCTURES HAVING FIN ISOLATION REGIONS BOUND BY GATE CUTS | ENAD, CHRISTINE A | 34d |
| 19033078 | INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK | MUNOZ, ANDRES F | 70d |
| 18649530 | MODULAR PRESS | NGUYEN, JIMMY T | 83d |
| Client (Assignee) | Pending OAs |
|---|---|
| Intel | 115 |
| USNR, LLC | 2 |
| Verve Group Inc. | 1 |
| Norwood Industries | 1 |
| APERA Al INC. | 1 |
| Art Unit | Apps |
|---|---|
| 2812 | 16 |
| 2818 | 10 |
| 2897 | 9 |
| 2893 | 8 |
| 2898 | 8 |
| 2899 | 7 |
| 2817 | 7 |
| 2874 | 7 |
| 2814 | 7 |
| 2811 | 5 |
| App # | Title | Client | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|---|
| 19033078 | INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK | Intel Corporation | MUNOZ, ANDRES F | 2818 | §103 | Final Rejection | 70d | AI Ready | Jan 21, 2025 |
| 18896711 | PRIVACY SUPPORTING MESSAGING SYSTEMS AND METHODS | Verve Group Inc. | STRAUB, D'ARCY WINSTON | 2491 | §103 | Non-Final OA | 5d overdue | Pending | Sep 25, 2024 |
| 18654739 | SAWMILL CARRIAGE, SAWMILL CARRIAGE KIT, AND METHOD OF USING SAME | Norwood Industries Inc. | LEE, LAURA MICHELLE | 3724 | §103 | Non-Final OA | 30d overdue | Pending | May 03, 2024 |
| 18649530 | MODULAR PRESS | USNR, LLC | NGUYEN, JIMMY T | 3725 | §112 | Non-Final OA | 83d | Pending | Apr 29, 2024 |
| 18611534 | GLASS CORE PATCH WITH IN SITU FABRICATED FAN-OUT LAYER TO ENABLE DIE TILING APPLICATIONS | Intel Corporation | SENGDARA, VONGSAVANH | 2893 | §102§103 | Non-Final OA | 15d | AI Ready | Mar 20, 2024 |
| 18438450 | INTEGRATED TOP SIDE POWER DELIVERY THERMAL TECHNOLOGY | Intel Corporation | VALENZUELA, PATRICIA D | 2812 | §103 | Non-Final OA | 34d | Pending | Feb 10, 2024 |
| 18390952 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES FABRICATED USING ALTERNATE ETCH SELECTIVE MATERIAL | Intel Corporation | KOO, LAMONT B | 2813 | §102§103 | Non-Final OA | 22d | AI Ready | Dec 20, 2023 |
| 18543784 | CONTACT OVER ACTIVE GATE STRUCTURES WITH CONDUCTIVE GATE TAPS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION | Intel Corporation | CHOI, CALVIN Y | 2812 | DPOther | Non-Final OA | 22d | AI Ready | Dec 18, 2023 |
| 18516595 | SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP | Intel Corporation | KOO, LAMONT B | 2813 | §102§103§112 | Non-Final OA | 40d | AI Ready | Nov 21, 2023 |
| 18376341 | BGA STIM PACKAGE ARCHITECTURE FOR HIGH PERFORMANCE SYSTEMS | Intel Corporation | BOYLE, ABBIGALE A | 2899 | §103§112 | Final Rejection | 19d | AI Ready | Oct 03, 2023 |
| 18374603 | SELECTIVE DIELECTRIC GROWTH FOR DIRECTING CONTACT TO GATE OR CONTACT TO TRENCH CONTACT | Intel Corporation | MICHAUD, ROBERT J | 2622 | §102 | Non-Final OA | 81d overdue | AI Ready | Sep 28, 2023 |
| 18374582 | INTEGRATING AND ACCESSING PASSIVE COMPONENTS IN WAFER-LEVEL PACKAGES | Intel Corporation | SYLVIA, CHRISTINA A | 2817 | §103 | Non-Final OA | 5d | AI Ready | Sep 28, 2023 |
| 18242322 | PACKAGE WITH EMBEDDED CAPACITORS | Intel Corporation | TRAN, TRANG Q | 2811 | §112 | Non-Final OA | 55d | AI Ready | Sep 05, 2023 |
| 18352111 | PRECUT PROCESSING OF LOGS | USNR, LLC | LINDSAY, BERNARD G | 2119 | §103 | Final Rejection | 73d overdue | Pending | Jul 13, 2023 |
| 18037517 | METHOD AND SYSTEM FOR IMAGE PROCESSING USING A VISION PIPELINE | Apera Al Inc. | WALLACE, JOHN R | 2682 | §103 | Non-Final OA | 77d overdue | Pending | May 17, 2023 |
| 18130328 | METHOD TO ACHIEVE TILTED PATTERNING WITH A THROUGH RESIST THICKNESS USING PROJECTION OPTICS | Intel Corporation | ABDELAZIEZ, YASSER A | 2898 | §103 | Final Rejection | 36d overdue | AI Ready | Apr 03, 2023 |
| 18129879 | SPRAY-COATED PHOTORESIST AND PHOTOIMAGEABLE DIELECTRICS TO ENABLE TSV BRIDGE FOR GLASS CORE PACKAGES | Intel Corporation | SABUR, ALIA | 2812 | §102§103 | Non-Final OA | 62d | Pending | Apr 02, 2023 |
| 18129400 | BACKSIDE TRANSISTOR CONTACT SURROUNDED BY OXIDE | Intel Corporation | CHAMBLISS, ALONZO | 2897 | §102§112 | Non-Final OA | 62d | Pending | Mar 31, 2023 |
| 18129258 | METAL INSULATOR METAL (MIM) CAPACITOR ARCHITECTURES | Intel Corporation | DIAZ, JOSE R | 2815 | §103 | Non-Final OA | 16d overdue | AI Ready | Mar 31, 2023 |
| 18193231 | CXL-CACHE/MEM PROTOCOL INTERFACE (CPI) LATENCY REDUCTION MECHANISM | Intel Corporation | LIN, AMIE CHINYU | 2436 | §101§102§103 | Non-Final OA | 27d | AI Ready | Mar 30, 2023 |
| 18126702 | BACK SIDE INTERCONNECT PATTERNING AND FRONT SIDE METAL INTERCONNECT ON A TRANSISTOR LAYER | Intel Corporation | LINDSAY JR, WALTER LEE | 2852 | §102§103 | Non-Final OA | 61d | Pending | Mar 27, 2023 |
| 18121720 | FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING TUNED UPPER NANOWIRES | Intel Corporation | VU, VU A | 2897 | §102§103 | Non-Final OA | 50d | Pending | Mar 15, 2023 |
| 18117818 | INTEGRATED ANTIOXIDANT AND SEALANT SOLUTION TO ADDRESS TEMPERATURE HUMIDITY RELIABILITY ISSUE OF LIQUID METAL INTERCONNECT | Intel Corporation | DINH, TUAN T | 2847 | §102§103 | Non-Final OA | 46d | Pending | Mar 06, 2023 |
| 18177426 | PHASE CURRENT BALANCE ARCHITECTURE FOR A MULTI-PHASE POWER CONVERTER | Intel Corporation | PHAN, RAYMOND NGAN | 2175 | §102§103§112 | Non-Final OA | 29d | AI Ready | Mar 02, 2023 |
| 18148578 | POWER MANAGEMENT FOR BATTERY GROUP | Intel Corporation | LEE, JAMES | 1725 | §102§103 | Non-Final OA | 61d | Pending | Dec 30, 2022 |
| 18091026 | ENABLING COPPER RECESS FLATTENING THROUGH BLOCKED COPPER ETCHING PROCESSES | Intel Corporation | CHOUDHRY, MOHAMMAD M | 2899 | §102§103DP | Non-Final OA | 56d | AI Ready | Dec 29, 2022 |
| 18091207 | CHARGE ISOLATION ARCHITECTURE IN VOLTAGE REGULATOR FOR IMPROVED BATTERY LIFE, RESPONSIVENESS AND REDUCED ACOUSTIC NOISE | Intel Corporation | NGUYEN, PHIL K | §102§103 | Non-Final OA | 3d overdue | AI Ready | Dec 29, 2022 | |
| 18090807 | INTEGRATED CIRCUIT STRUCTURES HAVING LAYER SELECT TRANSISTORS FOR SHARED PERIPHERALS IN MEMORY | Intel Corporation | LINDSEY, COLE LEON | 2812 | §103§112 | Non-Final OA | 9d overdue | AI Ready | Dec 29, 2022 |
| 18089886 | INTEGRATED CIRCUIT STRUCTURES HAVING TWO-TRANSISTOR GAIN CELL | Intel Corporation | NGUYEN, TUAN DUC | 2699 | §102§103 | Non-Final OA | 61d | AI Ready | Dec 28, 2022 |
| 18089908 | INTEGRATED CIRCUIT STRUCTURES HAVING STACKED ELECTROSTATIC DISCHARGE (ESD) FOR BACKSIDE POWER DELIVERY | Intel Corporation | VU, HUNG K | 2897 | §102§103 | Non-Final OA | 33d | AI Ready | Dec 28, 2022 |
| 18089471 | THIN FILM CAPACITOR (TFC) ARCHITECTURES FOR PACKAGE SUBSTRATES | Intel Corporation | PAYEN, MARVIN | 2899 | §102§103 | Non-Final OA | 34d | AI Ready | Dec 27, 2022 |
| 18089491 | LIQUID METAL WELLS FOR INTERCONNECT ARCHITECTURES | Intel Corporation | WOLDEGEORGIS, ERMIAS T | 2893 | §102§103 | Non-Final OA | 8d overdue | AI Ready | Dec 27, 2022 |
| 18089489 | SUBSTRATE GLASS CORE PATTERNING FOR CTV IMPROVEMENT AND LAYER COUNT REDUCTION | Intel Corporation | ESTRADA, ANGEL R | 2841 | §102 | Non-Final OA | 9d | AI Ready | Dec 27, 2022 |
| 18089501 | FUNCTIONALLY GRADED INDEX MOLD FOR CO-PACKAGED OPTICAL APPLICATIONS | Intel Corporation | CHIEM, DINH D | 2874 | §103 | Non-Final OA | 20d | AI Ready | Dec 27, 2022 |
| 18088543 | INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE POWER DELIVERY AND SIGNAL ROUTING FOR FRONT SIDE DRAM | Intel Corporation | ARORA, AJAY | 2892 | §103 | Non-Final OA | 29d | AI Ready | Dec 24, 2022 |
| 18088542 | GALLIUM NITRIDE (GAN) LAYER ON SUBSTRATE CARBURIZATION FOR INTEGRATED CIRCUIT TECHNOLOGY | Intel Corporation | TYNES JR., LAWRENCE C | 2899 | §103§112 | Non-Final OA | 26d overdue | AI Ready | Dec 24, 2022 |
| 18088541 | INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE HIGH | Intel Corporation | HO, ANTHONY | 2817 | §102§103 | Non-Final OA | 15d overdue | AI Ready | Dec 24, 2022 |
| 18088360 | CONFIGURABLE MICRO HEAT PIPE (MHP) AND MICROCHANNEL FOR IMPROVED COOLING OF GLASS CORE SUBSTRATE | Intel Corporation | CRUM, JACOB R | 2835 | §102§103§112 | Non-Final OA | 62d | AI Ready | Dec 23, 2022 |
| 18085116 | LAYER TRANSFER CLAMP FOR GALLIUM NITRIDE (GAN) INTEGRATED CIRCUIT TECHNOLOGY | Intel Corporation | BLACKWELL, ASHLEY NICOLE | 2897 | §103 | Non-Final OA | 36d overdue | AI Ready | Dec 20, 2022 |
| 18085258 | BRIDGE HUB TILING ARCHITECTURE | Intel Corporation | QUINTO, KEVIN V | 2893 | §103 | Non-Final OA | 72d | Pending | Dec 20, 2022 |
| 18076130 | LINED CONDUCTIVE STRUCTURES FOR TRENCH CONTACT | Intel Corporation | PAGE, STEVEN MITCHELL CHR | 2812 | §102 | Final Rejection | 19d overdue | AI Ready | Dec 06, 2022 |
| 18072564 | FABRICATION OF INTEGRATED CIRCUIT STRUCTURES HAVING UNIFORMITY AMONG VARYING GATE TRENCH WIDTHS | Intel Corporation | BEARDSLEY, JONAS TYLER | 2811 | §102§103 | Non-Final OA | 45d overdue | AI Ready | Nov 30, 2022 |
| 18071246 | INTEGRATED OPTICAL PHASE CHANGE MATERIALS FOR RECONFIGURABLE OPTICS IN GLASS CORES | Intel Corporation | PENG, CHARLIE YU | 2874 | §102 | Non-Final OA | 1d overdue | AI Ready | Nov 29, 2022 |
| 18071116 | RBTV IMPROVEMENT FOR GLASS CORE ARCHITECTURES | Intel Corporation | FAN, SU JYA | 2818 | §102§103 | Non-Final OA | 77d | Pending | Nov 29, 2022 |
| 17958291 | PLUG BETWEEN TWO GATES OF A SEMICONDUCTOR DEVICE | Intel Corporation | PRENTY, MARK V | 2814 | §102 | Non-Final OA | 9d | AI Ready | Sep 30, 2022 |
| 17958279 | GAIN CELL USING PLANAR AND TRENCH FERROELECTRIC AND ANTI-FERROELECTRIC CAPACITORS FOR EDRAM | Intel Corporation | IMTIAZ, S M SOHEL | 2812 | §103 | Non-Final OA | 13d | AI Ready | Sep 30, 2022 |
| 17958281 | DESIGN OF VOLTAGE CONTRAST PROCESS MONITOR | Intel Corporation | LOPEZ, JORGE ANDRES | 2897 | §103 | Non-Final OA | 38d overdue | AI Ready | Sep 30, 2022 |
| 17956779 | INTEGRATED CIRCUIT STRUCTURES HAVING FIN ISOLATION REGIONS RECESSED FOR GATE CONTACT | Intel Corporation | HAN, JONATHAN | 2818 | §103 | Non-Final OA | 32d overdue | AI Ready | Sep 29, 2022 |
| 17955511 | MUSHROOMED VIA STRUCTURES FOR TRENCH CONTACT OR GATE CONTACT | Intel Corporation | RAHMAN, MOHAMMAD A | 2898 | §102§103 | Non-Final OA | 12d | AI Ready | Sep 28, 2022 |
| 17955378 | OPTICAL COUPLER | Intel Corporation | RAHLL, JERRY T | 2874 | §102§103 | Non-Final OA | 15d overdue | AI Ready | Sep 28, 2022 |
| 17954194 | INTEGRATED CIRCUIT STRUCTURES HAVING FIN ISOLATION REGIONS BOUND BY GATE CUTS | Intel Corporation | ENAD, CHRISTINE A | 2811 | §103 | Final Rejection | 34d | AI Ready | Sep 27, 2022 |
| 17954292 | VERTICAL THROUGH-SILICON WAVEGUIDE FABRICATION METHOD AND TOPOLOGIES | Intel Corporation | DOAN, JENNIFER | 2874 | §102§103 | Non-Final OA | 14d | AI Ready | Sep 27, 2022 |
| 17954288 | IMPLANTATION OF SPECIES ON GLASS CORE SURFACE FOR LOW LOSS AND HIGH STRENGTH APPLICATIONS | Intel Corporation | CHEN, YU | 2896 | §102§103§112 | Non-Final OA | 26d | AI Ready | Sep 27, 2022 |
| 17954291 | NECKED RIBBON FOR BETTER N WORKFUNCTION FILLING AND DEVICE PERFORMANCE | Intel Corporation | MENZ, DOUGLAS M | 2897 | §102§103 | Non-Final OA | 69d | AI Ready | Sep 27, 2022 |
| 17953873 | HIGH ASPECT RATIO METAL GATE CUTS | Intel Corporation | TURNER, BRIAN | 2818 | §102§103 | Non-Final OA | 11d overdue | AI Ready | Sep 27, 2022 |
| 17953206 | ELECTROLYTIC SURFACE FINISH ARCHITECTURE | Intel Corporation | ROBINSON, KRYSTAL | 2848 | §102§103 | Non-Final OA | 28d overdue | AI Ready | Sep 26, 2022 |
| 17951995 | ALTERING OPERATIONAL CHARACTERISTICS OF A SEMICONDUCTOR DEVICE USING ACCELERATED IONS | Intel Corporation | FAYETTE, NATHALIE RENEE | 2812 | §102§103 | Non-Final OA | 5d overdue | AI Ready | Sep 23, 2022 |
| 17952017 | TESTING A SEMICONDUCTOR DEVICE USING X-RAYS | Intel Corporation | HOQUE, FARHANA AKHTER | 2858 | §102 | Final Rejection | 15d | AI Ready | Sep 23, 2022 |
| 17949857 | IC PACKAGE WITH LEDS | Intel Corporation | YEUNG LOPEZ, FEIFEI | 2899 | §103 | Non-Final OA | 7d | AI Ready | Sep 21, 2022 |
| 17895916 | THROUGH GLASS VIAS (TGVS) IN GLASS CORE SUBSTRATES | Intel Corporation | AHMADI, MOHSEN | 2896 | §102§103 | Non-Final OA | 25d overdue | AI Ready | Aug 25, 2022 |
| 17890005 | INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE POWER DELIVERY FOR MULTI-HEIGHT STANDARD CELL CIRCUITS | Intel Corporation | STEVENSON, ANDRE C | 2899 | §103 | Final Rejection | 72d | Pending | Aug 17, 2022 |
| 17887273 | SACRIFICIAL LAYER FOR SUBSTRATE ANALYSIS | Intel Corporation | BODNAR, JOHN A | 2893 | §102§103 | Non-Final OA | 28d overdue | AI Ready | Aug 12, 2022 |
| 17858031 | SEMICONDUCTOR PACKAGE HAVING PASSIVE SUPPORT WAFER | Intel Corporation | TRAN, THANH Y | 2817 | §102§103 | Final Rejection | 2d overdue | AI Ready | Jul 05, 2022 |
| 17855639 | CONTACT ARCHITECTURE FOR 2D STACKED NANORIBBON TRANSISTOR | Intel Corporation | OH, JIYOUNG | 2818 | §103§112 | Non-Final OA | 15d | AI Ready | Jun 30, 2022 |
| 17855636 | VOLTAGE CONTRAST SCAN AREA ON A WAFER | Intel Corporation | VALENZUELA, PATRICIA D | 2812 | §103 | Final Rejection | 79d | Pending | Jun 30, 2022 |
| 17853329 | DIE-STACKED AND MOLDED ARCHITECTURE FOR MEMORY ON PACKAGE (MOP) | Intel Corporation | PARTHASARATHY, ROHIT | 2899 | §103 | Final Rejection | 77d | AI Ready | Jun 29, 2022 |
| 17853500 | IN-SITU MULTI-LAYER DIELECTRIC FILMS FOR APPLICATION AS GATE SPACER AND ETCH STOP LAYERS | Intel Corporation | DUREN, TIMOTHY EDWARD | 2817 | §102§103 | Non-Final OA | 44d overdue | AI Ready | Jun 29, 2022 |
| 17851985 | INTEGRATED CIRCUIT STRUCTURES HAVING MEMORY WITH BACKSIDE POWER DELIVERY | Intel Corporation | TURNER, BRIAN | 2818 | §103 | Non-Final OA | 30d overdue | AI Ready | Jun 28, 2022 |
| 17850778 | INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE POWER STAPLE | Intel Corporation | HOANG, TUAN A | 2898 | §103 | Non-Final OA | 23d | AI Ready | Jun 27, 2022 |
| 17848630 | HYPER DENSITY PACKAGE SUBSTRATE AND MEMORY COUPLED TO A MODIFIED SEMI-ADDITIVE PROCESS BOARD | Intel Corporation | SRINIVASAN, SESHA SAIRAMAN | 2812 | §103 | Non-Final OA | 20d | AI Ready | Jun 24, 2022 |
| 17841550 | DYNAMIC INPUT POWER MONITOR | Intel Corporation | YEN, PAUL JUEI-FU | 2175 | §103 | Final Rejection | 85d overdue | AI Ready | Jun 15, 2022 |
| 17833568 | ULTRA-LASER THOUGH HOLE (ULTH) BY MULTI-STACKED CORE CONCEPT | Intel Corporation | FREAL, JOHN BRENDAN | 2847 | §103 | Non-Final OA | 71d | Pending | Jun 06, 2022 |
| 17833600 | MEMORY PACKAGE ON EXTENDED BASE DIE OVER SOC DIE FOR PACKAGE LAYER COUNT AND FORM FACTOR REDUCTION | Intel Corporation | ANDREWS, FELIX BRYAN | 2812 | §103 | Final Rejection | 120d overdue | AI Ready | Jun 06, 2022 |
| 17826933 | USB TYPE-C SUBSYSTEM | Intel Corporation | UNELUS, ERNEST | 2181 | §102§103 | Non-Final OA | 4d overdue | AI Ready | May 27, 2022 |
| 17716940 | TECHNIQUES FOR DIE TILING | Intel Corporation | JUNGE, BRYAN R. | 2897 | §103 | Non-Final OA | 69d | Pending | Apr 08, 2022 |
| 17710802 | DEVICE PERFORMANCE TUNING BY DEEP TRENCH VIA (DVB) PROXIMITY EFFECT IN ARCHITECTURE OF BACKSIDE POWER DELIVERY | Intel Corporation | ENAD, CHRISTINE A | 2811 | §102§103 | Final Rejection | 15d overdue | AI Ready | Mar 31, 2022 |
| 17709365 | LAYERED 2D SEMICONDUCTORS | Intel Corporation | FARMER, EMILY NICOLE | 2812 | §103 | Non-Final OA | 68d | Pending | Mar 30, 2022 |
| 17709360 | BARRIERS TO MODULATE UNDERFILL FLOW | Intel Corporation | BRASFIELD, QUINTON A | 2814 | §102§103 | Final Rejection | 41d | Pending | Mar 30, 2022 |
| 17707371 | PLASMA-INDUCED SURFACE FUNCTIONALIZATION OF SINX THIN FILM FOR IMPROVED ADHESION OF METAL-DIELECTRIC FOR HSIO | Intel Corporation | POWERS, LAURA C | 1785 | §103§112DP | Final Rejection | 1d overdue | AI Ready | Mar 29, 2022 |
| 17703730 | LOW PROFILE IMPEDANCE-TUNABLE AND CROSS-TALK CONTROLLED HIGH SPEED HYBRID SOCKET INTERCONNECT | Intel Corporation | PATEL, TULSIDAS C | 2834 | §102§103§112 | Non-Final OA | 42d | AI Ready | Mar 24, 2022 |
| 17694266 | FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DUAL METAL GATES AND GATE DIELECTRICS WITH A SINGLE POLARITY DIPOLE LAYER | Intel Corporation | SALAZ, SAMMANTHA KATELYN | 2892 | §103DP | Non-Final OA | 10d overdue | AI Ready | Mar 14, 2022 |
| 17693150 | FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADDITIVE GATE STRUCTURES IN A TUB ARCHITECTURE | Intel Corporation | CRAMER, HALEE PAIGE | 2891 | §103 | Non-Final OA | 42d overdue | AI Ready | Mar 11, 2022 |
| 17682804 | POWER GATE WITH METAL ON BOTH SIDES | Intel Corporation | SALERNO, SARAH KATE | 2814 | §103 | Non-Final OA | 21d | AI Ready | Feb 28, 2022 |
| 17561733 | 3D ARRAYED GLASS-BASED MMWAVE AND THZ STRUCTURES | Intel Corporation | TRAN, TIEN | 2812 | §103 | Non-Final OA | 5d overdue | AI Ready | Dec 24, 2021 |
| 17561735 | SUSPENDED STRUCTURES IN GLASS USING MODIFIED GLASS PATTERNING PROCESSES | Intel Corporation | MCCOY, THOMAS WILSON | 2814 | §103 | Non-Final OA | 3d overdue | AI Ready | Dec 24, 2021 |
| 17561720 | RECONSTITUTED WAFER-TO-WAFER HYBRID BONDING INTERCONNECT ARCHITECTURE WITH KNOWN GOOD DIES | Intel Corporation | ESIABA, NKECHINYERE OTUOMASIRICH | 2817 | §102§103 | Non-Final OA | 33d | AI Ready | Dec 24, 2021 |
| 17561686 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SOURCE OR DRAIN STRUCTURES WITH SUBSTRATE CONNECTION PORTIONS | Intel Corporation | HRNJIC, ADIN | 2817 | §103 | Non-Final OA | 1d overdue | AI Ready | Dec 23, 2021 |
| 17561681 | HIGH BANDWIDTH AND CAPACITY APPROACHES FOR STITCHED DIES | Intel Corporation | NGUYEN, CUONG B | 2818 | §103 | Non-Final OA | 5d overdue | AI Ready | Dec 23, 2021 |
| 17561682 | INTEGRATED CIRCUIT STRUCTURE WITH BURIED POWER RAIL | Intel Corporation | TRICE III, WILLIAM CLARENCE | 2893 | §103 | Non-Final OA | 23d | AI Ready | Dec 23, 2021 |
| 17558425 | COPPER-FILLED TRENCH CONTACT FOR TRANSISTOR PERFORMANCE IMPROVEMENT | Intel Corporation | LIN, JOHN | 2815 | §103 | Final Rejection | 141d overdue | AI Ready | Dec 21, 2021 |
| 17558046 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SOURCE OR DRAIN-LAST STRUCTURES | Intel Corporation | BERRY, PAUL ANTHONY | 2898 | §112 | Final Rejection | 131d overdue | AI Ready | Dec 21, 2021 |
| 17557932 | SEMICONDUCTOR STRUCTURE FOR NANORIBBON ARCHITECTURES | Intel Corporation | STEPHENSON, KENNETH STEPHEN | 2898 | §103 | Non-Final OA | 70d | Pending | Dec 21, 2021 |
| 17556660 | TECHNIQUES FOR DIE TILING | Intel Corporation | JUNGE, BRYAN R. | 2897 | §103 | Non-Final OA | 27d | AI Ready | Dec 20, 2021 |
| 17554442 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING RAISED WALL STRUCTURES FOR EPITAXIAL SOURCE OR DRAIN REGION CONFINEMENT | Intel Corporation | ADHIKARI DAWADI, BIPANA | 2898 | §103§112 | Non-Final OA | 45d overdue | AI Ready | Dec 17, 2021 |
| 17554456 | ISO-LEVEL VIAS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION | Intel Corporation | MILLER, ALEXANDER MICHAEL | 2898 | §103 | Non-Final OA | 13d | AI Ready | Dec 17, 2021 |
| 17553161 | INTEGRATED CIRCUIT STRUCTURES HAVING DIELECTRIC ANCHOR AND CONFINED EPITAXIAL SOURCE OR DRAIN STRUCTURE | Intel Corporation | MUNOZ, ANDRES F | 2818 | §102§103 | Non-Final OA | 9d | AI Ready | Dec 16, 2021 |
| 17485325 | OXIDE LAYER DOPING ON A SUB CHANNEL OF A TRANSISTOR STRUCTURE | Intel Corporation | MIHALIOV, DMITRI | 2812 | §103§112 | Final Rejection | 72d | AI Ready | Sep 25, 2021 |
| 17485232 | COMPLEX FIELD-SHAPING BY FINE VARIATION OF LOCAL MATERIAL DENSITY OR PROPERTIES | Intel Corporation | WINTERS, SEAN AYERS | 2892 | §103 | Final Rejection | 31d overdue | AI Ready | Sep 24, 2021 |
| 17485185 | THIN FILM TRANSISTORS HAVING CMOS FUNCTIONALITY INTEGRATED WITH 2D CHANNEL MATERIALS | Intel Corporation | GREWAL, HEIM KIRIN | 2812 | §103 | Final Rejection | 87d overdue | AI Ready | Sep 24, 2021 |
| 17485217 | PHYSICAL AND ELECTRICAL PROTOCOL TRANSLATION CHIPLETS | Intel Corporation | ANDERSON, WILLIAM H | 2817 | §103 | Final Rejection | 66d overdue | AI Ready | Sep 24, 2021 |
| 17484970 | TRANSISTOR STRUCTURE WITH A MONOLAYER EDGE CONTACT | Intel Corporation | RICHARDS, NORMAN DREW | 2892 | §103 | Final Rejection | 147d overdue | AI Ready | Sep 24, 2021 |
| 17482275 | FIRST LEVEL INTERCONNECT UNDER BUMP METALLIZATIONS FOR FINE PITCH HETEROGENEOUS APPLICATIONS | Intel Corporation | ONUTA, TIBERIU DAN | 2814 | §103 | Non-Final OA | 188d overdue | AI Ready | Sep 22, 2021 |
| 17481234 | MULTIPLE DIES COUPLED WITH A GLASS CORE SUBSTRATE | Intel Corporation | TRAN, TRANG Q | 2811 | §102§103 | Non-Final OA | 80d overdue | Pending | Sep 21, 2021 |
| 17481247 | DOUBLE-SIDED GLASS SUBSTRATE WITH A HYBRID BONDED PHOTONIC INTEGRATED CIRCUIT | Intel Corporation | BEDTELYON, JOHN M | 2874 | §102§103 | Non-Final OA | 28d | AI Ready | Sep 21, 2021 |
| 17481237 | GLASS CORE SUBSTRATE INCLUDING BUILDUPS WITH DIFFERENT NUMBERS OF LAYERS | Intel Corporation | ANDERSON, ERIK ARTHUR | 2812 | §103§112 | Non-Final OA | 11d overdue | AI Ready | Sep 21, 2021 |
| 17479031 | OPTICAL WAVEGUIDES WITHIN A GLASS SUBSTRATE TO OPTICALLY COUPLE DIES ATTACHED TO THE GLASS SUBSTRATE | Intel Corporation | JORDAN, ANDREW | 2874 | §103§112 | Non-Final OA | 23d overdue | AI Ready | Sep 20, 2021 |
| 17357767 | SUBSTRATE-LESS NANOWIRE-BASED LATERAL DIODE INTEGRATED CIRCUIT STRUCTURES | Intel Corporation | NGUYEN, DUY T V | 2818 | §103 | Non-Final OA | 16d | AI Ready | Jun 24, 2021 |
| 17357722 | UNIVERSAL HYBRID BONDING SURFACE LAYER USING AN ADAPTABLE INTERCONNECT LAYER FOR INTERFACE DISAGGREGATION | Intel Corporation | CAMPBELL, SHAUN M | 2893 | §103 | Final Rejection | 24d overdue | AI Ready | Jun 24, 2021 |
| 17350164 | CAPACITORS IN A GLASS SUBSTRATE | Intel Corporation | DOLE, TIMOTHY J | 2800 | §103 | Final Rejection | 79d | Pending | Jun 17, 2021 |
| 17350809 | PACKAGE WITH OPTICAL WAVEGUIDE IN A GLASS CORE | Intel Corporation | MANHEIM, MARC ETIENNE | 2874 | §103 | Final Rejection | 56d | AI Ready | Jun 17, 2021 |
| 17346990 | INTEGRATED CIRCUIT STRUCTURES HAVING METAL GATES WITH REDUCED ASPECT RATIO CUTS | Intel Corporation | HANUMASAGAR, SHAMITA S | 2814 | §103 | Non-Final OA | 11d overdue | Pending | Jun 14, 2021 |
| 17133080 | METAL LINE AND VIA BARRIER LAYERS, AND VIA PROFILES, FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION | Intel Corporation | KIM, JAHAE | 2897 | §103 | Final Rejection | 38d overdue | AI Ready | Dec 23, 2020 |
| 17129854 | METAL INSULATOR METAL (MIM) CAPACITOR WITH PEROVSKITE DIELECTRIC | Intel Corporation | SEHAR, FAKEHA | 2893 | §103 | Non-Final OA | 15d overdue | AI Ready | Dec 21, 2020 |
| 17129851 | PLATE LINE ARCHITECTURES FOR 3D-FERROELECTRIC RANDOM ACCESS MEMORY (3D-FRAM) | Intel Corporation | CORNELY, JOHN PATRICK | 2812 | §103 | Final Rejection | 88d overdue | AI Ready | Dec 21, 2020 |
| 17129846 | NOVEL LGA ARCHITECTURE FOR IMPROVING RELIABILITY PERFORMANCE OF METAL DEFINED PADS | Intel Corporation | NELSON, JACOB THEODORE | 2815 | §103 | Final Rejection | 89d overdue | AI Ready | Dec 21, 2020 |
| 17031719 | 3D HETEROGENEOUS INTEGRATED CRYSTALLINE PIEZOELECTRIC BULK ACOUSTIC RESONATORS | Intel Corporation | NGUYEN, THANH T | 2893 | §103 | Non-Final OA | 218d overdue | Pending | Sep 24, 2020 |
| 17020200 | TANDEM MAGNETICS IN PACKAGE | Intel Corporation | CHAN, TSZFUNG JACKIE | 2837 | §102§103 | Final Rejection | 98d overdue | AI Ready | Sep 14, 2020 |
| 16940117 | SOURCE/DRAIN CONTACTS FOR NON-PLANAR TRANSISTORS | Intel Corporation | BOULGHASSOUL, YOUNES | 2814 | §102 | Non-Final OA | 39d | AI Ready | Jul 27, 2020 |
| 16912136 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING STRAINED SOURCE OR DRAIN STRUCTURES ON GATE DIELECTRIC LAYER | Intel Corporation | XU, ZHIJUN | 2818 | §103 | Non-Final OA | 34d | AI Ready | Jun 25, 2020 |
| 15859415 | PITCH-DIVIDED INTERCONNECTS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION | Intel Corporation | MIYOSHI, JESSE Y | 2898 | §103 | Non-Final OA | 62d | AI Ready | Dec 30, 2017 |
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